1. Field of the Invention
The present invention relates generally to processing systems and, more specifically to processing systems with multi-core processing systems.
2. Background Art
In the past, increasing performance in processing-intensive electronic devices, such as base transceiver stations and other types of communications devices, could be achieved merely by increasing the processor clock speed of the devices. Since this approach is no longer practical, the use of multi-core systems has become a popular approach for increasing performance in processing-intensive electronic devices, such as base station transceivers. To realize the potential increase in performance that multiple processing cores can provide, however, each processing core needs to be programmed so that the processing workload is appropriately divided over all of the processing cores. However, programming multiple processing cores can be significantly more complicated than programming a single core.
Conventional multi-core systems can include, for example, one or more Reduced Instruction Set Computing (RISC) processors and a number of slave processing cores, such as digital signal processors (DSPs) and/or co-processors. A typical conventional approach for programming a multi-core system includes handling each processing core as an intelligent entity that communicates with others via a framework or multi-processor operating system. However, in this conventional approach the communication between the different processing cores must be explicitly handled. As a result, a programmer must be concerned with the number of slave processing cores in the multi-core system and the operation of each processing core, which places an undesirable burden on the programmer. Accordingly, there is a need in the art for a multi-core system that can effectively address the aforementioned difficulty of programming multiple slave processing cores in a conventional multi-core system.